1. Field of the Invention
This invention relates in general to metal-oxide-semiconductor (MOS) devices and, in particular, to inversion-mode MOS devices having dielectrically isolated semiconductor layers. More particularly, the present invention relates to a method for measuring the carrier generation lifetime and other parameters in these dielectrically isolated layers by using a dual-gate deep-depletion effect.
2. Description of the Prior Art
The quality of dielectrically isolated semiconductor layers is of critical importance in the operation of MOS devices employing these layers. The carrier generation lifetime of these layers is an important parameter in the device design and is also a good indication of layer quality since carrier lifetime is particularly sensitive to crystal quality and impurity concentrations. It would be very useful to have a convenient and accurate technique for lifetime measurement in order to develop clear-cut lifetime profiles as a function of deposition and processing parameters or monitor device quality.
For many reasons, lifetime is difficult to measure and results are difficult to interpret, especially in thin silicon films. In general, the presently available methods for measuring lifetime are not satisfactory for inversion-type devices. One commonly used technique to measure generation lifetime is the transient deep-depletion capacitance technique (F. P. Heiman, "On the determination of minority carrier lifetime from the transient response of an MOS capacitor," IEEE Trans. Electron Devices, vol. ED-14, pp. 781-784, Nov. 1967), in which a large-area MOS capacitor is pulsed into depletion. Generation lifetime is found by monitoring the capacitance change of the structure with time as an inversion layer becomes established under the MOS gate. This technique is not well suited for thin semiconductor films in which the depletion region width is comparable to the layer thickness, because series-resistance effects between the edges and the center of the capacitor seriously degrade measurement accuracy. In addition, the large size required of the MOS capacitor for good measurement accuracy may preclude its use as a test device on most integrated circuit chips.
Another technique previously used for generation lifetime measurement in thin silicon films was developed by Kamins (T. I. Kamins, "Minority carrier lifetime in dielectrically isolated single-crystal silicon films defined by electrochemical etching," Solid-State Electron., vol. 17, pp. 675-681, 1974), using deep-depletion MOS transistors. In such devices, there are no p-n junctions, and current flow occurs in the undepleted bulk of the transistor body. In such a structure, a depletion-type voltage pulse on the upper gate of the transistor will constrict the channel region, reducing drain current. As an inversion layer is established under the gate by bulk thermal generation, surface generation, or photoinjection, the depletion width decreases and the channel region widens. Lifetime can be estimated by monitoring the drain current. Since this technique is a single-gate technique, it is a useful method for measuring lifetime in deep-depletion devices but is not suitable for inversion-type devices.